It is known to use a RAM to provide the functions of one or more FIFOs for buffering signals between an isochronous (constant rate) source or sink and an asynchronous (variable rate) sink or source. For example, in a communications system speech or data signals may be supplied from a tdm (time division multiplex) bus, at a constant rate of one byte in each frame for each channel, being written into a FIFO for the respective channel at this rate, and may be read asynchronously from the FIFO under the control of a processor. The size, or depth, of the FIFO may be one or more bytes, depending on the system and the sensitivity of the signals to delay. Conversely, the signals may be written asynchronously into the FIFOs and read isochronously from the FIFOs. As these two arrangements are equivalent, only the former is described further below, it being understood that corresponding comments apply equally to the latter.
For addressing the RAM to store the isochronous signals in the appropriate FIFOs, it is necessary to provide control hardware, desirably in the form of an integrated circuit. To this end, it is known for the control hardware to store, in registers for each FIFO, at least a base address for the location of the FIFO in the RAM, a depth of the FIFO, and a write pointer identifying the next location in the FIFO for storage of a signal. A read pointer is likewise required for reading from the FIFO.
For a large number of FIFOs and a large RAM, the storage required for the control hardware becomes considerable and inconvenient to provide in an integrated circuit. For example, for writing into 1024 FIFOs each up to 1024 bytes deep in a 1 Mbyte RAM, each FIFO requires 20 bits for the base address, 10 bits for the read pointer, and 10 bits for the FIFO depth, so that the control hardware requires a total storage capacity of 40K bits. This requires a large area of an integrated circuit, consumes a lot of power, operates relatively slowly because of the memory accesses which are required, and necessitates a long time for testing.
An object of this invention is to provide an improved arrangement for providing FIFOs in RAM, which allows many FIFOs of variable sizes to be provided without the above disadvantages of the prior art.